RESEARCH INTO THE ARCHITECTURE OF A SOFTWARE-HARDWARE COMPLEX FOR IMPLEMENTING POST-QUANTUM ALGORITHMS IN EMBEDDED SYSTEMS

DOI: 10.31673/2409-7292.2025.041217

Abstract

The article considers the theoretical, structural and algorithmic foundations of implementing post-quantum
cryptographic methods in hardware-software complexes (HPCs) of embedded security systems. The need to transition to
cryptographic solutions resistant to quantum attacks is substantiated, and an analysis of the effectiveness of the main algorithms
standardized by NIST is provided. A conceptual hierarchical architecture of the HPC is developed, which ensures the
implementation of cryptographic operations in real time under conditions of limited resources. Mathematical models of the
encryption, verification and key exchange processes are proposed, and analytical metrics of time and energy efficiency are
presented. Special attention is paid to the analysis of hardware accelerators and their impact on the performance of cryptographic
operations, which allows to significantly reduce time delays compared to software implementations. It is determined that the
use of specialized NTT modules and optimized modular arithmetic mechanisms forms the basis for the effective integration of
post-quantum algorithms into microcontroller platforms. The PAK resistance to side-channel attacks and operational
disturbances was assessed, which allows for the formulation of comprehensive requirements for the security of such systems.
The paper also considers the features of adapting cryptographic protocols to different classes of embedded processors, including
RISC-V and ARM architectures. This ensures the versatility of the proposed approach. The results demonstrate the possibility
of building scalable and energy-efficient PAKs capable of providing reliable information protection in the face of increasing
requirements for stability and performance.
Keywords: post-quantum cryptography; embedded systems; software-hardware complex; energy efficiency;
cryptographic acceleration; hardware architecture.

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